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A PRACTICAL GUIDE FOR SYSTEMVERILOG ASSERTIONS IBD

MEYYAPPAN RAMANATHAN / SRIKANTH VIJAYARAGH
SPRINGER
12 / 2014
9781489992796
Inglés

Sinopsis

SystemVerilog language consists of threeácategories of featuresá-- Design, Assertions and Testbench.á Assertions add a whole new dimension to the ASIC verification process.áááEngineers are used to writing testbenches in verilog that helpáverify their design.á Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today.á SystemVerilog assertions (SVA) is a declarative language.á The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously.á This provides theáengineers a very strong tool to solve their verification problems.á The language is still new and the thinking is very different from theáuserâÇÖs perspective when compared to standard verilog language.á There is not enough expertise or intellectual property available as of today in the field.á While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.á This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.

PVP
207,34€